// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/8/24
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// *******************
// DESCRIPTION
// *******************
// 将宽度32深度33的ram改为寄存器，加快查找速率
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 


module queue_infor_length_w16_d5_reg(
input  wire            clk       , // input clka
input  wire            wea       , // input  [0 : 0] wea
input  wire [2 : 0]    addra     , // input  [5 : 0] addra
input  wire [15: 0]    dina      , // input  [16: 0] dina
output reg  [15: 0]    douta     , // output [16: 0] douta
input  wire            rst_n     , // input rst_n
input  wire            web       , // input  [0 : 0] web
input  wire [2 : 0]    addrb     , // input  [5 : 0] addrb
input  wire [15: 0]    dinb      , // input  [16 : 0] dinb
output reg  [15: 0]    doutb     
 );
reg [15:0]      queue_infor_reg_0 ;
reg [15:0]      queue_infor_reg_1 ;
reg [15:0]      queue_infor_reg_2 ;
reg [15:0]      queue_infor_reg_3 ;
reg [15:0]      queue_infor_reg_4 ;



//输出
always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        douta <= 16'd0;
    end
    else if (wea) begin
        douta <= douta;
    end
    else begin
        case (addra)
        3'd0  : begin
            douta <= queue_infor_reg_0 ;
        end 
        3'd1  : begin 
            douta <= queue_infor_reg_1 ;
        end 
        3'd2  : begin 
            douta <= queue_infor_reg_2 ;
        end 
        3'd3  : begin 
            douta <= queue_infor_reg_3 ;
        end 
        3'd4  : begin 
            douta <= queue_infor_reg_4 ;
        end 
        default: begin
            douta <= douta;
        end
        endcase
    end
end

always @(posedge clk or negedge rst_n) begin
    if(~rst_n) begin
        doutb <= 16'd0;
    end
    else if (web) begin
        doutb <= doutb;
    end
    else begin
        case (addrb)
        3'd0  : begin
            doutb <= queue_infor_reg_0 ;
        end 
        3'd1  : begin 
            doutb <= queue_infor_reg_1 ;
        end 
        3'd2  : begin 
            doutb <= queue_infor_reg_2 ;
        end 
        3'd3  : begin 
            doutb <= queue_infor_reg_3 ;
        end 
        3'd4  : begin 
            doutb <= queue_infor_reg_4 ;
        end 
        default: begin
            doutb <= doutb;
        end
        endcase
    end
end

//reg 信息维护
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_0 <= 16'b0;
    end
    else if ((addra == 3'd0) && wea && (addrb == 3'd0) && web) begin
        queue_infor_reg_0 <= dina + dinb - queue_infor_reg_0;
    end
    else if ((addra == 3'd0) && wea) begin
        queue_infor_reg_0 <= dina;
    end
    else if((addrb == 3'd0) && web) begin
        queue_infor_reg_0 <= dinb;
    end
    else begin
        queue_infor_reg_0 <= queue_infor_reg_0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_1 <= 16'b0;
    end
    else if ((addra == 3'd1) && wea && (addrb == 3'd1) && web) begin
        queue_infor_reg_1 <= dina + dinb - queue_infor_reg_1;
    end
    else if ((addra == 3'd1) && wea) begin
        queue_infor_reg_1 <= dina;
    end
    else if((addrb == 3'd1) && web) begin
        queue_infor_reg_1 <= dinb;
    end
    else begin
        queue_infor_reg_1 <= queue_infor_reg_1;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_2 <= 16'b0;
    end
    else if ((addra == 3'd2) && wea && (addrb == 3'd2) && web) begin
        queue_infor_reg_2 <= dina + dinb - queue_infor_reg_2;
    end
    else if ((addra == 3'd2) && wea) begin
        queue_infor_reg_2 <= dina;
    end
    else if((addrb == 3'd2) && web) begin
        queue_infor_reg_2 <= dinb;
    end
    else begin
        queue_infor_reg_2 <= queue_infor_reg_2;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_3 <= 16'b0;
    end
    else if ((addra == 3'd3) && wea && (addrb == 3'd3) && web) begin
        queue_infor_reg_3 <= dina + dinb - queue_infor_reg_3;
    end
    else if ((addra == 3'd3) && wea) begin
        queue_infor_reg_3 <= dina;
    end
    else if((addrb == 3'd3) && web) begin
        queue_infor_reg_3 <= dinb;
    end
    else begin
        queue_infor_reg_3 <= queue_infor_reg_3;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        queue_infor_reg_4 <= 16'b0;
    end
    else if ((addra == 3'd4) && wea && (addrb == 3'd4) && web) begin
        queue_infor_reg_4 <= dina + dinb - queue_infor_reg_4;
    end
    else if ((addra == 3'd4) && wea) begin
        queue_infor_reg_4 <= dina;
    end
    else if((addrb == 3'd4) && web) begin
        queue_infor_reg_4 <= dinb;
    end
    else begin
        queue_infor_reg_4 <= queue_infor_reg_4;
    end
end


endmodule